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Chapter 14: AltLab Library
14–9
HIL (Hardware in the Loop)
The HIL (Hardware in the Loop) block allows you to use an FPGA as a simulation
device inside a Simulink design. This configuration accelerates the simulation time,
and also allows access to real hardware in a simulation.
To use an HIL block, you need an FPGA development board with a JTAG interface.
Use any JTAG download cable, such as a ByteBlasterMV?, ByteBlaster?, or
USB-Blaster? cable.
HIL supports advanced features, including:
■
■
Exported ports (allows the use of hardware components connected to the FPGA)
Burst mode (improves HIL simulation speed)
1
This block supports only single clock designs with registered paths in a design. The
simulation results may be unreliable for combinational paths.
Table 14–12 shows the parameters specified in page 1 of the HIL dialog box.
Table 14–12. HIL Block Parameters, Page 1
Name
Select the Quartus II
project
Select the clock pin
Select the reset pin
Identify the signed
ports
Export
Select the reset level
Burst Mode
Burst Length
Sampling Period
Assert “Sclr” before
starting the simulation
Value
. qpf file
Port name
Port name
Signed or
Unsigned
On or Off
Active_High,
Active_Low
On or Off
(1)
Integer
On or Off
Description
Browse for a Quartus II project file ,which describes the hardware design that the
HIL block uses.
The clock pin name for the hardware design in the Quartus II software.
The reset pin name for the hardware design in the Quartus II software.
Set the number of bits and select the type (signed or unsigned) of each input and
output port in the hardware design.
When on, the selected port is exported on an FPGA pin (or on multiple pins for
buses). When off (the default), the port is exported to the Simulink model.
The reset level that matches the setting in the original design. For designs originated
from the standard blockset, the reset level is specified in the Clock or
Clock_Derived block. If your design uses no clock block, it uses a default clock
with reset level active high. For designs originated from the advanced blockset, the
reset level is specified in the Signals block.
When on, allows sending data to the FPGA in bursts, which improves the simulation
speed, but delays the outputs by the burst length. When Off, it defaults to
single-step mode.
Specify the length of a burst ("1" is equivalent to disabling burst mode). Use higher
values to produce faster simulations (although the extra gain becomes negligible
with bigger burst sizes).
Specify the sample time period in seconds. (A value of -1 means that the sampling
period is inherited from the block connected to the inputs.)
When on, asserts the synchronous clear signal before the simulation starts.
Note to Table 14–12 :
(1) The record size is 32×1024×1024, which is the product of ( packet size ) × ( burst length ) while the packet size is the larger of the total input data
width and the total output data width. For example, for a packet size of 1024 bits, set the burst length to 32×1024. However, due to the
limitations of the JTAG interface, the optimal record size is between 1 to 2 MBPS (depending on the host computer, USB driver and cables).
Hence, setting a bigger burst size might not give significant speed up.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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